Autores UPV
Ghiribaldi Alberto,
DANIELE LUDOVICI,
Triviño García Francisco,
ALESSANDRO STRANO,
Flich Cardo José,
JOSÉ LUIS SÁNCHEZ GARCÍA,
F. J. ALFARO,
Favalli Michele,
DAVIDE BERTOZZI
Abstract
Networks-on-chip need to survive to manufacturing faults in order to sustain yield. An effective testing and
configuration strategy however implies two opposite requirements. One one hand, a fast and scalable built-in
self-testing and self-diagnosis procedure has to be carried out concurrently at NoC switches. On the other
hand, programming the NoC routing mechanism to go around faulty links and switches can be optimally
performed by a centralized controller with global network visibility. To the best of our knowledge, this article
proposes for the first time a global network testing and configuration strategy that meets the opposite
requirements by means of a fault-tolerant dual network architecture and a fast configuration algorithm for
the most common failure patterns.
Experimental results report an area overhead as low as 12.5% with respect to the baseline switch architecture
while achieving a high degree of fault tolerance. In fact, even when multiple stuck-at faults are
considered, the capability of fault masking by the dual network is always over 80%, and the support for multiple
link failures is more than 90% in presence of two unusable links in the main network with minimum
set-up times.
