Abstract
This paper proposes a low-complexity min-sum algorithm
for decoding low-density parity-check codes. It is an improved
version of the single-minimum algorithm where the twominimum
calculation is replaced by one minimum calculation and
a second minimum emulation. In the proposed one, variable correction
factors that depend on the iteration number are introduced
and the second minimum emulation is simplified, reducing by this
way the decoder complexity. This proposal improves the performance
of the single-minimum algorithm, approaching to the normalized
min-sum performance in the water-fall region. Also, the
error-floor region is analyzed for the code of the IEEE 802.3an
standard showing that the trapping sets are decoded due to a slow
down of the convergence of the algorithm. An error-floor free operation
below BER is shown for this code by means of a
field-programmable gate array (FPGA)-based hardware emulator.
A layered decoder is implemented in a 90-nm CMOS technology
achieving 12.8 Gbps with an area of 3.84 mm .
